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Job Responsibilities:

• Designing instruction sets and commands for a massively parallel high-performance computer system.
• Designing data flow pathways for moving data within a massively parallel system efficiently and reliably
• Optimizing parallel computing architectures for optimal performance on purpose built machines.
• Designing arithmetic logic units for efficient pipelined processing. ·
• Interacting with customers, both internal and external, to convey architecture principles and concepts.
• Efficient and effective communication of design and architecture to digital designers for implementation, simulation and synthesis.

Required Education:

• Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or other relevant technology field with 5 years of relevant experience (3 years with an MS; none with a PhD).

-OR-

• Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or other relevant technology field with 9 years of relevant experience (7 years with an MS; 4 with a PhD).

Required Experience:

• Experience with VHDL.
• Experience with C and/or Matlab.
• Previous HW or SW design experience is required.

Desired Experience:

• Ability to use, configure, and manager a Cadence Design
• Previous experience with other aspects of the design process, from design point through tape out through test and acceptance.
• A Master's Degree or a PhD in related field is highly desirable.