All Qualified Resumes Responded to in 24 Hrs or Less
Active DOD Secret Clearance or Eligible 
#CJ

Job Duties:

• Work closely with the design team streamlining the design flow and improving the efficiency
• License and hardware server usage and tracking
• LSF support for the hardware engineering compute cluster
• EDA tool approval requests
• installation, testing, supporting module file creation
• PDK update installations
• 3rd party IP installations and License installations

 

Required Education:

• Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 5+ years of ASIC experience, (MS with 3+ years experience)

-OR-

• Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 9+ years of ASIC experience, (MS with 7+ years or PhD with 4+ experience)

 

Required Skills:

• Experience with some of the following: IC design tools (e.g. – Cadence or  Mentor): Genus, Innovus, Tempus, Calibre, Jasper, Conformal
• Experience interfacing with engineers and managers to schedule projects and to provide schedule updates and roadmaps.
• Experience with account management in Git and JIRA
• Strong written and oral communication skills are required.

 

Desired Skills:

• Proficiency in the entire ASIC design flow from RTL through tape-out (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
• Tool experience with Formal verification Synopsys Formality or Cadence Conformal
• Familiarity with EDA standards used in cell/library development and modeling – Liberty, LEF (library exchange format), DEF (design exchange format), OA (OpenAccess)