Physical Layout Design Engineer

Linthicum, MD

Physical Layout Design Engineer

Create custom layouts including: Process Control Monitor (PCM) structures, reticle alignment marks, and physical measurement structures. Mentoring and guidance are provided by process engineers, photo lithography engineers and layout peers.
Provide layout floor planning.
Create chip designs in various processes for process prove-in, experimentation, and test support.
Perform layout verifications of designs.
Participate in reticle composition and tape out activities.
Document work performed.

Additional Valuable Skills:

Experience using Cadence design suite of tools to perform full and semi-custom layout.
- Knowledge of Cadence Virtuoso L/XL/EXL capabilities that enhance layout task efficiency.
- The ability to make minor schematic edits to support the layout effort.
Knowledge of semiconductor device physics and analog/mixed signal integrated circuit design.
Experience laying out or characterizing digital standard cells or memory elements.
Layout simulation using tools such as ANSYS/HFSS or ADS.
Building scripts, in an agreed upon programing language, to automate repetitive tasks or facilitate an increase in productive work.
Create and document flows for future re-use and quality control.
Knowledge of an industry programing language: Shell, Python, Perl, TCL/TK or equivalent.
Experience with any of the following:
- Behavior modeling skills using Verilog-A or Verilog-AMS.
- Full-chip functional/performance verification methods.
Experience collaborating with research staff/quantum physicists to realize proof of principle layouts.

Preferred Qualifications:

Understanding of the Semiconductor fabrication process and process development.
Understanding of Process Design Kit (PDK) Development (tech files, verification rule files, Pcells, skill programing)
Skilled in the use of the Cadence Virtuoso L layout and schematic capture tools.
Proficient in the use of Cadence ASSURA and Mentor Calibre DRC/LVS verification tools.
Experience in Superconducting Reciprocal Quantum Logic circuit design layout practices