All qualified resumes responded to in 24HRs or less
Applicants must be US citizens 
All work will be preformed on-site 

These are Full time Direct positions, Consuting may be an option on a case by case sinerio 
Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 12 years of relevant experience (10 years with technical MS; 7 years with PhD) - Experience in HDL (VHDL/Verilog) and HVL (SystemVerilog)
Experience with SystemVerilog Assertions (SVA)
Knowledge of Universal Verification Methodology (UVM)
Familiarity with a coverage driven verification methodology from planning through closure
Knowledge of industry standard interfaces
Experience with object oriented programming languages and concepts
US Citizen and able to obtain and maintain a clearance.
Preferred Qualifications Staff Digital Verification Engineer:

Advanced Degree either MS or PhD
Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience
Experience with scripting languages (Bash, Perl, Python, Tcl)

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